Strong Pull-ups on FPGAs - JTAG Boundary-Scan Test Tip

Introduction

Many FPGAs in their preconfigured state include relatively strong internal
pull-up/pull-downs, often in the 4.7k-ohm range or lower. If a weak
pull-up/pull-down resistor is attached to such a pin, there is risk that the
pull-up/pull-down test may fail.

Explanation

Consider the simplified diagram below:

Figure 1: 10k Pull-down attached to a pre-configuration
BIDIR FPGA pin

The pre-configuration boundary-scan pin has an effective internal pull-up
resistance of 4.7k-ohms. It is externally strapped with a weak 10k-ohm pull-down
resistor. Driving the net will not be a problem—when the output buffer is
enabled, current will flow through either resistor, allowing the output node to
be driven and sensed both HIGH and LOW.

However, the pull-up/pull-down test will tri-state the output of this pin and
then expect the 10k pull-down to take the value (as sensed by the input cell)
down to “0”. This is not the case—let’s determine why.

Voltage Dividers

When the output buffer tri-states, we end up with a simple voltage divider
between the internal effective resistance and the external pull-down. We can
calculate the value here:

Vpd = Vcc * Rext/(Rext + Rint) = Vcc * 10k/(4.7k + 10k) ~= 0.7Vcc

This is a very high value and will likely not meet the VIL requirements, causing
the resistor test to fail, possibly intermittently.

Resolution

When this situation occurs, the best solution may be to remove the net from
testing during the resistor test. While—depending on resistor values—it may be
on the border of meeting the threshold requirements and often sense LOW, it is
probable that it will not be reliable and cause false test failures. In reality
the pull-down should be considered un-testable by boundary-scan
pull-up/pull-down test methods.

Source: JTAG Boundary-Scan Test Tip: Strong Pull-ups on FPGAs