Using BSDL

When a board is designed, boundary-scan-compliant devices are organized into “chains”. Scan chains form the basis for system-level and board-level tests that are capable of detecting and diagnosing pin-level structural faults such as opens and shorts. Automated tools are used to generate test programs or procedures circuit boards. The most important inputs to this process are the BSDL files for JTAG devices and the netlist that describes the interconnects between the devices of the circuit board. The generated test program, when applied to a target board, reports structural test failures and can be used to assist in QA and board repair.

Some tools are capable in utilizing boundary-scan for creation of test patterns for component clusters which include non-boundary-scan-compliant devices. Some tools can generate test patterns which on-board processors can run to enable at-speed functional testing. These test procedures can be stand-alone or applied in conjunction with other test techniques, such as In-Circuit Testing (ICT), with the ultimate goal of producing optimal test coverage at low cost and with short development time.