Thursday, November 20, 2008

What is BSDL?

The Boundary-Scan Description Language enables users to provide a description of the way in which boundary-scan is implemented in any particular device. As each chip designer tends to apply the boundary-scan standard in a slightly different way, it is necessary to express tests in a comprehensible, specific and usable fashion.

BSDL is written within a subset of VHDL. VHDL is commonly used as a design-entry language for FPGAs and ASICs in electronic design automation of digital circuits, and as such it is suitable for work with boundary-scan since design of many chips is performed using this language. However BSDL is a "subset and standard practice" of VHDL, i.e., the scope of VHDL is thereby limited for boundary-scan application.

During the design of BSDL there were two main criteria for the language:

  • It should be easy to use
  • It should be parsable by a computer in a simple and unambiguous fashion
BDSL enables accurate and useful descriptions of the features of a device that uses boundary-scan. The BSDL file is used by the boundary-scan tools to make use of the device features to enable test program generation, failure diagnosis, as well as use in any testability analysis. BSDL is not a language that can be used for hardware description; rather, it is used to define the data transport characteristics of the device, i.e. how it captures, shifts, and updates scanned data. This is then used in defining the test capability. The BSDL file includes the following data:

  • Entity Declaration: The Entity Declaration is a VHDL construct that is used to identify the name of the device that is described by the BSDL file.
  • Generic Parameter: The Generic Parameter is the section that specifies which package is described.
  • Logical Port Description: This description lists all the connections on the device. It defines its basic attributes, i.e., whether the connection is an input (in bit;), output (out bit;), bi-directional (inout bit;) or if it is unavailable for boundary-scan (linkage bit;).
  • Package Pin Mapping: The Package Pin Mapping is used for determining the internal connections within an integrated circuit. It details how the pads on the device die are wired to the external pins.
  • Use Statements: This statement is used to call the VHDL packages that contain the data that are referenced in the BSDL File.
  • Scan Port Identification: The Scan Port Identification identifies the particular pins that are used for the boundary-scan / JTAG implementation. These include: TDI, TDO, TMS, TCK and TRST (if used).
  • Test Access Port (TAP) Description: This entity provides additional information on the boundary-scan or JTAG logic for the device. The data includes the instruction register length, instruction opcodes, device IDCODE, etc.
  • Boundary Register Description: This description provides the structure of the boundary-scan cells on the device. Each pin on a device may have up to three boundary-scan cells, each cell consisting of a register and a latch.

Source: BSDL Tutorial


John said...
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Artur said...

It is worth of mentioning that BSDL files are used by most of JTAG (Boundary Scan) tools for automatic detection of scan chain configuration (recognizing devices on the chain and their supported BS instructions). Probably the largest collection of BSDL files is freely available online at