Why are JTAG Tools needed?
In the previous paragraph we listed all the benefits that a designer enjoys when using boundary-scan in his product development. In this section we will describe the tools and design data needed to develop JTAG test procedures and patterns for in-circuit programming. We will use a typical board as an illustration for the various JTAG test functions needed. A block diagram of such a board is depicted in Figure 4.
Figure 4 - Typical Board with JTAG Components
A typical digital board with JTAG devices includes the following main components:
- Various JTAG components such as CPLDs, FPGAs, Processors, etc., chained together via the boundary-scan path.
- Non-JTAG components (clusters).
- Various types of memory devices.
- Flash Memory components.
- Transparent components such as series resistors or buffers.
A typical boundary-scan test system is comprised of two basic elements: Test Program Generation and Test Execution. Generally the Test Program Generator (TPG) requires the netlist of the Unit Under Test (UUT) and the BSDL files of the JTAG components. The TPG automatically generates test patterns that allow fault detection and isolation for all JTAG testable nets of the printed circuit board (PCB). The TPG also creates test vectors to detect faults on the pins of non-scannable components such as clusters and memories that are surrounded by scannable devices.
Corelis TPGs also provide the user with a test coverage report, that allows the user to focus on the non-testable nets and determine what additional means are needed to increase the test coverage.
Test programs are generated in seconds. For example when Corelis ScanPlusExpressTPG was used, it took a 200MHz Pentium PC eight (8) seconds to generate an interconnect test for a UUT with 4,090 nets (with17,500 pins). This generation time includes netlist and all other input files processing, as well as test pattern file generation.
The test execution tool provides means for executing JTAG tests and perform in-circuit-programming in a pre-planned specific order called a test plan. Test vectors files, which have been generated using the TPG, are automatically applied to the UUT and the results are compared to the expected values. In case of a detected fault, the system diagnoses the fault and lists the failures as depicted in Figure 6. Different test plans may be constructed for different UUTs. Tests within a test plan may be re-ordered, enabled or disabled, and unlimited different tests can be combined into a test plan. Corelis test execution tool (ScanPlus Runner) also includes a test executive that is used to develop a test sequence or test plan from various independent sub tests. These sub tests can then be executed sequentially as many times as specified or continuously if desired. A sub test can also program CPLDs and Flash memories. For in-circuit programming other formats such as SVF, JAM, J-Drive and STAPL are also supported.
Figure 5 shows the ScanPlus Runner main window. As can be seen, ScanPlus Runner gives a user an overview of all test steps and the results of executed tests. These results are displayed both for individual tests as well as for the total test runs executed. ScanPlus Runner provides the ability to add or delete various test steps from a test plan, or re-arrange the order of the test steps in a plan. Tests can also be enabled or disabled, and the test execution can be stopped upon the failure of any particular test.
To test the board depicted in Figure 4, the user must execute a test plan that consists of various test steps as shown in Figure 5.
Figure 5 - ScanPlus Runner Main Window
The first and most important test is the scan-chain integrity test. The scan chain must work correctly prior to proceeding to other tests and in-system programming. Following a successful testing of the scan chain, the user can proceed to testing all the interconnects between the JTAG components. If the interconnect test fails, the ScanPlus Runner will display a diagnostic screen that will identify the type of the failure (such as stuck at, Bridge, Open) and will list the failing nets and pins as shown in Figure 6. Once the interconnect test passes, including the testing of transparent components, it makes sense to continue testing the clusters and the memory devices. At this stage the system is ready for in-circuit programming that usually is takes more time compared to the testing.
Figure 6 - ScanPlus Runner Diagnostics Display
During the design phase of a product, some JTAG vendors will provide design assistance in selecting JTAG compatible components, work with the developers to ensure that the proper BSDL (Boundary-scan Description Language) files are used, and provide advice in designing the product for testability.
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