JTAG Hacking

A JTAG enthusiast writes of his experience using JTAG to de-brick a router with corrupted firmware. JTAG is used to basically get access to the chips containing corrupted firmware and reprogram/reset code in the memory.

Read about it here:
http://www.networkworld.com/community/node/38699

iNEMI Boundary-Scan Adoption Survey

iNEMI wants to hear about your experiences with boundary scan. Whether you work with printed circuit boards and use the technology (e.g., are a PCB designer, test engineer, engineering manager, design-for-test consultant, service & support staff, system architect, test equipment provider, etc.) or are an IC designer who integrates boundary scan into your products - iNEMI wants to hear from you. iNEMI is gauging the adoption rate of boundary scan and identifying any impediments to widespread use. Your input can provide valuable feedback to help improve test implementation and coverage for electronic products.

Click here to take the survey.

How to Embed BSDL File Names in the Board Schematics and Netlist with Cadence OrCAD Capture

This article explains how to use the Cadence OrCAD Capture program to embed the BSDL file names in the schematics. The BSDL file name and package information will then be included in the packages section of a Telesis format netlist when it is created by OrCAD Capture.

EMA Currents - Winter 2008 Edition

TMAG Testability Management Action Group

The Testability Management Action Group (TMAG) is a grass roots organization made up of test professionals who believe that success for Testability in general, and Design for Testability (DFT) in particular, requires the involvement and the support of management at all levels.

We commend them for their hard work in DFT.

TMAG Testability Management Action Group

DFT Digest

DFT Digest is a weblog about electronics Design-for-Test to discuss state-of-the-art DFT methods, technologies and best-practices, with the ultimate aim of better understanding design-for-test through the increased participation of the greater DFT community.

They are starting to offer tutorial materials and links to resources on DFT there: DFT Digest

Popular BSDL Files

Corelis, a JTAG test vendor, now offers BSDL files for boundary-scan compatible devices to popular semiconductor vendors and their BSDL files.

You can locate the links and request form page here: BSDL file

Using BSDL

When a board is designed, boundary-scan-compliant devices are organized into “chains”. Scan chains form the basis for system-level and board-level tests that are capable of detecting and diagnosing pin-level structural faults such as opens and shorts. Automated tools are used to generate test programs or procedures circuit boards. The most important inputs to this process are the BSDL files for JTAG devices and the netlist that describes the interconnects between the devices of the circuit board. The generated test program, when applied to a target board, reports structural test failures and can be used to assist in QA and board repair.

Some tools are capable in utilizing boundary-scan for creation of test patterns for component clusters which include non-boundary-scan-compliant devices. Some tools can generate test patterns which on-board processors can run to enable at-speed functional testing. These test procedures can be stand-alone or applied in conjunction with other test techniques, such as In-Circuit Testing (ICT), with the ultimate goal of producing optimal test coverage at low cost and with short development time.