Tuesday, December 16, 2008

TMAG Testability Management Action Group

The Testability Management Action Group (TMAG) is a grass roots organization made up of test professionals who believe that success for Testability in general, and Design for Testability (DFT) in particular, requires the involvement and the support of management at all levels.

We commend them for their hard work in DFT.

TMAG Testability Management Action Group

Monday, December 15, 2008

DFT Digest

DFT Digest is a weblog about electronics Design-for-Test to discuss state-of-the-art DFT methods, technologies and best-practices, with the ultimate aim of better understanding design-for-test through the increased participation of the greater DFT community.

They are starting to offer tutorial materials and links to resources on DFT there: DFT Digest

Tuesday, December 2, 2008

Popular BSDL Files

Corelis, a JTAG test vendor, now offers BSDL files for boundary-scan compatible devices to popular semiconductor vendors and their BSDL files.

You can locate the links and request form page here: BSDL file

Monday, December 1, 2008

Using BSDL

When a board is designed, boundary-scan-compliant devices are organized into “chains”. Scan chains form the basis for system-level and board-level tests that are capable of detecting and diagnosing pin-level structural faults such as opens and shorts. Automated tools are used to generate test programs or procedures circuit boards. The most important inputs to this process are the BSDL files for JTAG devices and the netlist that describes the interconnects between the devices of the circuit board. The generated test program, when applied to a target board, reports structural test failures and can be used to assist in QA and board repair.

Some tools are capable in utilizing boundary-scan for creation of test patterns for component clusters which include non-boundary-scan-compliant devices. Some tools can generate test patterns which on-board processors can run to enable at-speed functional testing. These test procedures can be stand-alone or applied in conjunction with other test techniques, such as In-Circuit Testing (ICT), with the ultimate goal of producing optimal test coverage at low cost and with short development time.