Wednesday, October 29, 2008

What is JTAG


JTAG (also known as boundary-scan) has enjoyed growing popularity for board level manufacturing test applications since its introduction as an industry standard in 1990. JTAG has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and IC level access capabilities of JTAG, its use has expanded beyond traditional board test applications into product design and service.

This overview provides a brief overview of the JTAG architecture and the new technology trends that make using JTAG essential for dramatically reducing development and production costs. The article also describes the various uses of JTAG and its application.

JTAG, as defined by the IEEE Std. 1149.1 standard, is an integrated method for testing interconnects on printed circuit boards that is implemented at the IC level. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the same time.

In the 1980s, the Joint Test Action Group (JTAG) developed a specification for JTAG testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement that contains a description of the boundary-scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. Now, due to its economic advantages, smaller companies that cannot afford expensive in-circuit testers are using JTAG.

The boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes. It adds a boundary-scan cell that includes a multiplexer and latches, to each pin on the device. Boundary-scan cells in a device can capture data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the boundary-scan cells. All of this is controlled from a serial data path called the scan path or scan chain. Figure 1 depicts the main elements of a JTAG device. By allowing direct access to nets, JTAG eliminates the need for large number of test vectors, which are normally needed to properly initialize sequential logic. Tens or hundreds of vectors may do the job that had previously required thousands of vectors. Potential benefits realized from the use of JTAG are shorter test times, higher test coverage, increased diagnostic capability and lower capital equipment cost.

Figure 1 - Main Elements of a JTAG Device

The principles of interconnect test using JTAG are illustrated in Figure 2. Figure 2 depicts two JTAG compliant devices, U1 and U2 that are connected with four nets. U1 includes four outputs that are driving the four inputs of U2 with various values. In this case we will assume that that the circuit includes two faults: A short between Nets 2 and 3, and an open on Net 4. We will also assume that a short between two nets behaves as a wired-AND and an open is sensed as logic 1. To detect and isolate the above defects, the tester is shifting into the U1 boundary-scan register the patterns shown in Figure 2 and applying these patterns to the inputs of U2. The inputs values of U2 boundary-scan register are shifted out and compared to the expected results. In this case the results (marked in red) on Nets 2, 3, and 4, do not match the expected values and therefore the tester detects the faults on Nets 2, 3, and 4.

JTAG tool vendors provide various types of stimulus and sophisticated algorithms to not only detect the failing nets but also isolate the faults to a specific nets, devices, and pin numbers.

Interconnect Test Example
Figure 2 - Interconnect Test Example

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