Tuesday, November 18, 2008

Questions about JTAG Boundary Scan?

JTAG: What topics interest you or would you like to read about? Comments?


John said...

How about some tutorial on BSDL, and how to generate it for a device that will go on a board?

DFT Digest

JohnTEaton said...

Well if you really want questions

1) How do designers create their boundary scan logic and bsdl file? Do you use commercial tools or home grown scripts?

2) What do you do with the trst_n pin? do you pull it up or down?

3) How are designers extending jtag to include on chip instrumentation bist etc.

4) Why is the safe bit for a control cell required to match the disable state?

5) Where can you get good inexpensive jtag probes and software

John Eaton